S. K. Lahiri: MNOS/Floating-Gate Charge Coupled Devices for High Density EEPROMs: A New Concept, Physics of Semiconductor Devices, V. Kumar and S. K. Agarwal (eds.), Narosa Publishing House, New Delhi, India, 1998, pages 951–956, the basic idea of CCD EEPROMS is known. Particularly, this conference paper discloses the general idea to arrange EEPROM gate structures each having a floating and a control (CCD) gate above a substrate in rows separated by rails of active areas or injectors provided in said substrate. However, S. K. Lahiri fails to disclose a suitable memory address scheme for such a CCD EEPROM taking into consideration a dynamic clocking. Moreover, this document also fails to disclose appropriate cells layouts and operation modi.
For example, CCD devices are known from W. S. Boyle, G. E. Smith: Charge Coupled Semiconductor Devices. The Bell System Technical Journal. American Telephone and Telegraph Company: New York, April 1970. Pages 587–593; Rudolf Müller: Bauelemente der Halbleiter-Elektronik. Springer Verlag: Berlin, Heidelberg, New York, London, Paris, Tokyo 1987. Seiten 192–195; Kurt Hoffmann: VLSI-Entwurf. Modelle und Schaltungen. Oldenbourg Verlag: München, Wien 1996. Seiten 296–297; and Lev I. Berger: Semiconductor Materials. CRC-Press: 1997. Page 445.
EEPROM devices are generally well known in the state of the art. EEPROM cells are used to store information, which should be still accessible after switching the power supply off and on again, while being able to modify the stored information multiple times by pure electrical means. EEPROM cells usually have source and drain contacts forming a MOS transistor. Information is read out by measuring the attributes of the output characteristic, which is dependent of the information stored in a gate structure having floating and control gate.
The overall transfer characteristic (programming conditions to read current) is highly nonlinear and strong dependent on several side effects and production fluctuations. I.e. the Fowler Nordheim tunneling current is more than exponentially dependent on the electric field across the oxide. So the programming voltage and the oxide thickness have severe influence on the programming process. Thus, these parameters must be adjusted with high precision. These accuracy problems limit the multilevel ability of known cell concepts to 2 bits per cell.
Fast cells are critical and must be handled with complex algorithms. Usually, only cells of a single wordline can be programmed at the same time. During sensing, there is a static current consumption through S and D of the MOS transistor. During parallel programming of cells in the test phase, there is a static current due to the gate induced drain leakage, which must be supplied by a charge pump. This current driving pump is area consuming.
Using drain and source contacts, the cell area of typical cells in embedded EEPROM modules results in 22*F2 to 70*F2. The world record for cells with drain and source contacts is 8.8*F2.
Nowadays new applications for non-volatile memories are borne, one of that is the possibility to store photos or music in solid state device. In this kind of application is required a sequential data access to the memory.